1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to a semiconductor chip package and a method of fabricating a semiconductor chip package that reduces chip size package (CSP).
2. Description of the Related Art
There is an increasing demand for small-sized and lightweight electronic system units. In order to satisfy such demands, efforts have been made to reduce the size of semiconductor chips by decreasing circuit wire width and by reducing semiconductor chip package size. The structure and fabrication method of a conventional semiconductor chip package will now be explained with reference to FIGS. 1A to 1E.
As illustrated in FIG. 1E, a semiconductor chip 12 adheres to an upper center portion of a substrate 10 of a semiconductor chip package by an adhesive 13. One side edge of a multi-layer wiring 11, which is formed on the substrate 10, is connected to a pad (not shown) on the semiconductor chip 12 by a wire 14. A liquid sealing material 17 having a high viscosity surrounds the semiconductor chip 12, the wire 14 and the one side edge of the multi-layer wiring 11. A solder resist 18 covers an upper portion of the other side edge of the multi-layer wiring 11, and a solder ball 19 is mounted on a predetermined portion thereof.
The fabrication method of the conventional semiconductor chip package as shown in FIG. 1E will now be explained.
First, as shown in FIG. 1A, the substrate 10 of the semiconductor chip package is prepared. The substrate 10 of the semiconductor chip package has a groove at its upper center portion. The multi-layer wiring 11 is formed on the substrate 10 outside the groove. The solder resist 18 covers the entire upper surface except for the one-side edge of the multi-layer wiring 11. After the substrate 10 is thus prepared, the unit semiconductor chip 12 is separated (by sawing, for example) from a wafer and is mounted on the groove of the substrate 10 using the adhesive 13.
As shown in FIG. 1B, the pad (not shown) on the upper surface of the semiconductor chip 12 is connected to the one side edge of the multi-layer wiring 11 by the wire 14.
As shown in FIG. 1C, a dam 16 is formed with a liquid resin having a sufficiently high viscosity at a predetermined portion of the multi-layer wiring 11 using a dispenser 15.
As shown in FIG. 1D, the semiconductor chip 12, the wire 14 and one side edge of the multi-layer wiring 11 inside the dam 16 are sealed by the liquid sealing material 17.
As shown in FIG. 1E, the solder resist 18 on the multi-layer wiring 11 is partially etched and removed, and a solder ball 19 is mounted thereon by a reflow process.
However, in the conventional package fabrication method, the substrate of the semiconductor package and the semiconductor chip are separately fabricated, and then the semiconductor chip is mounted on the substrate. As a result, the completed semiconductor chip package is thick and big. Thus, the semiconductor chip package does not provide small-sized and lightweight electronic systems. Also, the fabrication cost of the package also increases because the substrate for the semiconductor package is separately fabricated.